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• #9837 S_x96x_S addikt

  Új Válasz 2024-08-20 22:03:31 #9837

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  S_x96x_S

  addikt

  Fix 3Ghz-en, hogyan teljesítenek a CPU-k.

  "Zen 5 Variants and More, Clock for Clock"
  https://chipsandcheese.com/2024/08/20/zen-5-variants-and-more-clock-for-clock/
  
  ....

  "I hope AMD will increase the L1 instruction cache’s size later on. Going to 64 KB probably isn’t enough. Apple and Qualcomm have gone for very large 192 KB L1 instruction caches, and with good reason. But even that won’t be enough to contain the instruction footprint on certain workloads.

  Data-side latency is a big issue too. Tackling the memory latency problem today is arguably even harder than it was in the early 2010s. Pointer chasing through a 1 GB array with 2 MB pages gives about 76 ns of latency on the Athlon II X4 651. Do the same on the Ryzen AI 9 HX 370, and you’ll see over 128 ns of latency. Even though mobile Zen 5 has more reordering capacity and better caching than Husky, both cores often find themselves very backend bound.
  "

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