/Zen5?/
AMD's attempt to tackle the much debated x86's decode width issue aka x86 cannot increase decode width without massive power/area penalty:
Instead of one unit decoding many more instructions than what they have with multiple fast/slow paths, they are attempting multiple fetch-decode units decoding in parallel different branch windows of the instruction stream. Both pipelines are not active always, only when one pipeline cannot handle the instruction stream anymore.
Instructions gets decoded in parallel on all pipelines and gets reordered before dispatch if needed.
20220100519 - PROCESSOR WITH MULTIPLE FETCH AND DECODE PIPELINES
https://www.freepatentsonline.com/y2022/0100519.html
20220100663 - PROCESSOR WITH MULTIPLE OP CACHE PIPELINES
https://www.freepatentsonline.com/y2022/0100519.html
20220100501 - Compressing Micro-Operations in Scheduler Entries in a Processor
https://www.freepatentsonline.com/y2022/0100501.html
[link]
Találgatunk, aztán majd úgyis kiderül..
