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• #2460 Petykemano veterán

  Új Válasz 2021-08-19 12:33:52 #2460

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  Petykemano

  veterán

  Golden Cove fronend:

  "6D 8U 512R
  It means that:
  6 Simple Decoder (not include Complex Decoder)
  8 uops/cycle
  512 entries ReOrder buffers.
  Let we see. I have more information but I can't release it."
  
  
  Decoders:
  M1:
  Featuring an 8-wide decode block, Apple’s Firestorm is by far the current widest commercialized design in the industry.
  Other contemporary designs such as AMD’s Zen(1 through 3) and Intel’s µarch’s, x86 CPUs today still only feature a 4-wide decoder designs (Intel is 1+3) that is seemingly limited from going wider at this point in time due to the ISA’s inherent variable instruction length nature, making designing decoders that are able to deal with aspect of the architecture more difficult compared to the ARM ISA’s fixed-length instructions. On the ARM side of things, Samsung’s designs had been 6-wide from the M3 onwards, whilst Arm’s own Cortex cores had been steadily going wider with each generation, currently 4-wide in currently available silicon, and expected to see an increase to a 5-wide design in upcoming Cortex-X1 cores.
  ( [link] )
  
  (Én mondjuk úgy emlékszem, hogy a Sunny Cove 5 decoders)

  Re-order buffer (ROB)
  A +-630 deep ROB is an immensely huge out-of-order window for Apple’s new core, as it vastly outclasses any other design in the industry. Intel’s Sunny Cove and Willow Cove cores are the second-most “deep” OOO designs out there with a 352 ROB structure, while AMD’s newest Zen3 core makes due with 256 entries, and recent Arm designs such as the Cortex-X1 feature a 224 structure.
  ( [link] )

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