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  • #8947 S_x96x_S addikt
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    S_x96x_S

    addikt

    avx10 - újabb infók :
    a cél
    - az inkonzisztencia csökkentése
    - és a több regiszterből valamaint a K-maszkokból eredő sebességnövekedés.
    https://www.theregister.com/2023/08/15/avx10_intel_interviews/

    (intel) Van de Ven notes the new spec should address many of the frustrations raised by Torvalds back in 2020. "We listened very carefully to his feedback… part of his gripe was inconsistency," he said. "Inconsistency makes it harder for people to use it, and, if it's hard to use, it doesn't get used."
    In terms of implementation, Van de Ven told The Register that once fully fleshed out, most applications should be able to take advantage of the new SIMD instructions with nothing more than a recompile. Though, of course, Intel says it will provide additional tools for the one percent that want to further optimize their code.
    Another benefit of decoupling these features from AVX-512 is lower power overhead. "In terms of power and thermals, the extra registers and K-masks make the same code more efficient. That gives you a performance benefit, but the performance benefit is also a power benefit," Van de Ven said. "As an example, if your matrix multiply is suddenly 10 percent faster, you take 10 percent less time; your total power consumption is down by give or take 10 percent."
    ...

    Beyond a wider register width, AVX-512 has a couple of advantages over AVX2, SSE, and other SIMD instructions. Two of the biggest, according to Intel Fellow Arjan van de Ven, are its 32 registers, twice that of AVX2, and the introduction of K-masks. "A lot of the performance comes from those extra registers [and] from the K-masks; not so much the rest," he said.

    Under the new spec, AVX10 compatible chips will, for the most part, share a common feature set
    — including 32 registers, k-masks, FP16 support
    — and minimally support 256 bit wide registers.

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