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• #3738 S_x96x_S addikt

  Új Válasz 2020-08-28 15:53:49 #3738

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  S_x96x_S

  addikt

  Surprising new feature in AMD Ryzen 3000 ( agner.org )
  HN: https://news.ycombinator.com/item?id=24302057

  Agner:
  "I have just finished testing the AMD Zen 2 CPU.
  ...
  I discovered that the Zen 2 has a new surprising feature that we have never seen before: It can mirror the value of a memory operand inside the CPU so that it can be accessed with zero latency.
  
  This assembly code shows an example:

  mov dword [rsi], eax
add dword [rsi], 5
mov ebx, dword [rsi]

  When the CPU recognizes that the address [rsi] is the same in all three instructions, it will mirror the value at this address in a temporal internal register. The three instructions are executed in just 2 clock cycles, where it would otherwise take 15 clock cycles.
  
  It can even track an address on the stack while compensating for changes in the stack pointer across push, pop, call, and return instructions. This is useful in 32-bit mode where function parameters are pushed on the stack. A simple function can read its parameters without waiting for the values to be stored on the stack and read back again. This does not work if the stack pointer is modified by any other instructions or copied to a frame pointer. Therefore, it doesn't work with functions that set up a stack frame.
  
  The mechanism works only under certain conditions. It must use general purpose registers, and the operand size must be 32 or 64 bits. The memory operand must use a pointer and optionally an index. It does not work with absolute or rip-relative addresses.
  
  It seems that the CPU makes assumptions about whether memory operands have the same address before the addresses have been calculated. This may cause problems in case of pointer aliasing. If the second instruction in the above example has a different pointer register with the same value, you have a problem of pointer aliasing. The CPU assumes that the addresses are different so that the value of eax is directly forwarded to ebx without adding 5. It takes 40 clock cycles to undo the mistake and redo the correct calculation.
  
  Yet, this is a pretty amazing feature. Imagine how complicated it is to implement this in hardware without adding any latency. I wonder why this feature is not mentioned in any AMD documents or promotion material. At least, I can't find any mentioning of this anywhere. AMD has something they call superforwarding, but this must be something else because it applies only to floating point registers.

  ....
  "

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