''...
Processor Caches
Level 1
Code 12 K µOP Trace Cache, 8-Way, 6 µOPs/Line,
microcode is inserted both into and after TC,
the built traces span accross taken branches,
SMC on 4 KB granularity flushes the entire TC
Data 8 KB, 4-Way, 64 Byte/Line, MESI,
1 Line/Sector, Write-Through, Pseudo-LRU,
Non-blocking (up to 4 Load Misses),
Virtually Addressed, Physically Tagged,
Dual-ported (1 Load and 1 Store),
2/9 Cycle Latency (Integer/FP),
16 Byte Path to FP Unit for Loads ''
hobizoli
több drón kell ;P
