Inclusive: a cache (L1) tartalma az elozo fokozatban (L2) is megvan (data copy), atmasolja az adatokat, ujat nem tolt a helyere
Exclusive: nincs adatatfedes a ket szint kozott (data move), a helye felszabadul, igy ujabb adatokat lehet betolteni a helyere
K7:
''Processor Caches:
Level 1:
Code 64 KB, 2-Way, 64 Byte/Line, SI, LRU,
3 Pre-decode Bits/Byte (adds 24 KB)
Data 64 KB, 2-Way, 64 Byte/Line, MOESI, LRU,
Dual-ported, Write-Allocate, Multi-banked
Level 2:
Unified (Models 1/2)
On-Cartridge 512 KB..8 MB, 64 Byte/Line, Inclusive
On-Die Tags for 512 KB 2-Way (512 KB, 1 MB, or 2 MB) Direct-Mapped (4 MB and larger)
Unified (Model 3/7/8)
On-Die 64 KB, 16-Way, 64 Byte/Line, Exclusive
Unified (Model 4/6/8)
On-Die 256 KB, 16-Way, 64 Byte/Line, Exclusive
Unified (Model 10)
On-Die 512 KB, 16-Way, 64 Byte/Line, Exclusive''
1: Athlon Classic K7, 0.25µm
2: Athlon Classic K75, 0.18µm
3: Duron Spitfire, 0.18µm
4: Athlon Thunderbird, 0.18µm
6: Athlon Palomino, 0.18µm
7: Duron Morgan, 0.18µm
8: Duron Applebred/Athlon Thoroughbred, 0.13µm
10: Athlon Thorton/Barton, 0.13µm
P4:
''Processor Caches:
Level 1:
Code 12 K µOP Trace Cache, 8-Way, 6 µOPs/Line,
microcode is inserted both into and after TC,
the built traces span accross taken branches,
SMC on 4 KB granularity flushes the entire TC
Data 8 KB, 4-Way, 64 Byte/Line, MESI,
1 Line/Sector, Write-Through, Pseudo-LRU,
Non-blocking (up to 4 Load Misses),
Virtually Addressed, Physically Tagged,
Dual-ported (1 Load and 1 Store),
2/9 Cycle Latency (Integer/FP),
16 Byte Path to FP Unit for Loads
Level 2:
Unified (0.18 µm) Celeron
128 KB, 4-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Exclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
7/7 Cycle Latency (Integer/FP),
256 Bit Bus, Data on every Cycle
Unified (0.18 µm) non-Celeron
256 KB, 8-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Exclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
7/7 Cycle Latency (Integer/FP),
256 Bit Bus, Data on every Cycle
Unified (0.13 µm) Celeron
128 KB, 2-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Exclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
7/7 Cycle Latency (Integer/FP),
256 Bit Bus, Data on every Cycle
Unified (0.13 µm) mobile Celeron
256 KB, 4-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Exclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
7/7 Cycle Latency (Integer/FP),
256 Bit Bus, Data on every Cycle
Unified (0.13 µm) non-Celeron
512 KB, 8-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Exclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
7/7 Cycle Latency (Integer/FP),
256 Bit Bus, Data on every Cycle
Level 3 (selected parts):
Unified (0.18 µm) 512 KB, 4-Way, 64 Byte/Line, MESI,
1024 KB, 8-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Inclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
14/14 Cycle Latency (Integer/FP)
Unified (0.13 µm) 1024 KB, 8-Way, 64 Byte/Line, MESI,
2048 KB, 8-Way, 64 Byte/Line, MESI,
2 Lines/Sector,Inclusive, Pseudo-LRU,
Non-blocking, 64 GB cacheable,
14/14 Cycle Latency (Integer/FP)''
Egyidoben a CPU cache szintjeiben oszzesentarolhato adat:
K8: L1:128k; L2:1024k -> 128k+1024k=1152k
P4EE: L1: 8k; L2:512k; L3:2048k -> 2048k-512k+8k=1544k
:DD:C
hobizoli
[Szerkesztve]
több drón kell ;P