hdl: hardware description language
(verilog, vhdl, stb., stb.).
Írsz egy programot, ami leírja, hogy fog működni a tervezendő hardver, a progi meg ''legyártja'' neked, akár kapcsrajz szintig is. Persze némileg bonyolultabb lesz, mint a kézi design, de hát sokszor így tervezni (a procik tervezési ideje sokszorosa a gpukénak pl.). Kb. úgy, mint egy magasszintű és egy assembly viszonya.
A programozás természetesen nem úgy történik, hogy ''itt legyen egy pipeline'', hanem meglehetősen alacsony (logikai) szinten.
Íme egy példa egy USB vezérlő HDL leírásából (verilogban):
`include ''usb_defines.v''
module utmi_if( // UTMI Interface (EXTERNAL)
phy_clk, rst,
DataOut, TxValid, TxReady,
RxValid, RxActive, RxError, DataIn,
XcvSelect, TermSel, SuspendM, LineState,
OpMode, usb_vbus,
// Internal Interface
rx_data, rx_valid, rx_active, rx_err,
tx_data, tx_valid, tx_valid_last, tx_ready,
tx_first,
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached,
resume_req
);
input phy_clk;
output rst;
output [7:0] DataOut;
output TxValid;
input TxReady;
input [7:0] DataIn;
input RxValid;
input RxActive;
input RxError;
output XcvSelect;
output TermSel;
output SuspendM;
input [1:0] LineState;
output [1:0] OpMode;
input usb_vbus;
output [7:0] rx_data;
output rx_valid, rx_active, rx_err;
input [7:0] tx_data;
input tx_valid;
input tx_valid_last;
output tx_ready;
input tx_first;
output mode_hs; // High Speed Mode
output usb_reset; // USB Reset
output usb_suspend; // USB Suspend
output usb_attached; // Attached to USB
input resume_req;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [7:0] rx_data;
reg rx_valid, rx_active, rx_err;
reg [7:0] DataOut;
reg tx_ready;
reg TxValid;
wire drive_k;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
///////////////////////////////////////////////////////////////////
//
// RX Interface Input registers
//
always @(posedge phy_clk)
if(!rst) rx_valid <= #1 0;
else rx_valid <= #1 RxValid;
always @(posedge phy_clk)
if(!rst) rx_active <= #1 0;
else rx_active <= #1 RxActive;
always @(posedge phy_clk)
if(!rst) rx_err <= #1 0;
else rx_err <= #1 RxError;
always @(posedge phy_clk)
rx_data <= #1 DataIn;
///////////////////////////////////////////////////////////////////
//
// TX Interface Output/Input registers
//
wire tx_valid_sr;
assign tx_valid_sr = (!rst) ? 0 : tx_valid_last ? 1 : TxReady ? 0 : tx_valid_sr;
always @(posedge phy_clk)
if(TxReady | tx_first) DataOut <= #1 tx_data;
else
if(drive_k) DataOut <= #1 8'hff;
always @(posedge phy_clk)
tx_ready <= #1 TxReady;
always @(posedge phy_clk)
TxValid <= #1 tx_valid | tx_valid_sr | drive_k;
while (!sleep) sheep++;